<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>SystemVerilog on 兜忆轩 | Cedric's Compiler Notes</title><link>https://douyixuan.github.io/tags/systemverilog/</link><description>Recent content in SystemVerilog on 兜忆轩 | Cedric's Compiler Notes</description><image><title>兜忆轩 | Cedric's Compiler Notes</title><url>https://douyixuan.github.io/images/papermod-cover.png</url><link>https://douyixuan.github.io/images/papermod-cover.png</link></image><generator>Hugo -- 0.146.0</generator><language>en-us</language><lastBuildDate>Wed, 07 Oct 2026 12:38:00 +0800</lastBuildDate><atom:link href="https://douyixuan.github.io/tags/systemverilog/index.xml" rel="self" type="application/rss+xml"/><item><title>022 · 断言被证明后，谁证明它值得验证？</title><link>https://douyixuan.github.io/posts/ai-silicon-papers/2026-10-07/</link><pubDate>Wed, 07 Oct 2026 12:38:00 +0800</pubDate><guid>https://douyixuan.github.io/posts/ai-silicon-papers/2026-10-07/</guid><description>ProofLoop 让 Agent 查询 RTL 结构并利用形式反例修正 SVA，显著提高可证明断言的比例；但在 Design2SVA 中，性质成立、性质非空洞与性质重要仍是三个不同判断。</description></item><item><title>021 · 六类任务拼在一起，就算端到端验证了吗？</title><link>https://douyixuan.github.io/posts/ai-silicon-papers/2026-10-06/</link><pubDate>Tue, 06 Oct 2026 12:36:00 +0800</pubDate><guid>https://douyixuan.github.io/posts/ai-silicon-papers/2026-10-06/</guid><description>FIXME 用 180 道题覆盖规格理解、参考模型、测试用例、testbench、断言和调试；它拓宽了 LLM 硬件验证评测，却也留下一个概念边界：流程覆盖不等于端到端执行。</description></item></channel></rss>