https://douyixuan.github.io/tags/rtl-generation/Recent content in RTL-Generation on 兜忆轩 | Cedric's Compiler Noteshttps://douyixuan.github.io/images/papermod-cover.pnghttps://douyixuan.github.io/images/papermod-cover.pngHugo -- 0.146.0en-usMon, 21 Sep 2026 12:22:00 +0800https://douyixuan.github.io/posts/ai-silicon-papers/2026-09-21/Mon, 21 Sep 2026 12:22:00 +0800https://douyixuan.github.io/posts/ai-silicon-papers/2026-09-21/ChipVerilog 把 RTL 生成评测推进到长模块和跨模块层级：强模型大多能生成可编译代码，但功能正确率随规模与层级迅速下降；这也暴露了规格来源和验证口径的边界。